X60
Shipping in K1The edge AI core: 8-core coherent clusters at 2 GHz on TSMC 22 nm, about 35% lower power than same-class rivals. The first 8-core RISC-V AI CPU in volume.
>3.5 SPEC2006/GHz · 2 GHz @ 22 nm
Key Stone K1 and K3
K3 runs 30B-parameter models on device. K1 is the world's most popular RISC-V AI CPU.
| Key Stone K1 | Key Stone K3 | |
|---|---|---|
| CPU config | 8 × X60, up to 2.0 GHz | 8 × X100 + 8 × A100, up to 2.4 GHz |
| Peak integer compute | 50K DMIPS | 130K DMIPS · over 9.0 SPECint2006/GHz per core |
| AI compute | 2.0 TOPS fused in the CPU cores | 60 TOPS INT4 · BF16 / FP16 / FP8 / INT8 / INT4 |
| ISA profile | RVA22 · RVV 1.0 256-bit | RVA23 · RVV 1.0 1024-bit · Hypervisor + AIA + IOMMU |
| Process node | TSMC 22 nm | TSMC 12 nm |
| Memory | LPDDR4X 2400 MT/s · boards carry 8 to 16 GB | LPDDR5 6400 MT/s · boards carry 16 to 32 GB |
| Video codecs | Hardware VPU decode · 4K playback | Decode 4K120 · encode 4K60 |
| Target workloads | SBCs · robots · edge LLM terminals · NAS · industrial terminals | AI computers · embodied robots · personal and edge AI servers · LLM inference |
Compute cores
One core line spans every chip above. Each generation doubles the integer throughput per gigahertz.
X100
Shipping in K3The first RISC-V processor core with full virtualization support: 12-stage, 4-wide out-of-order, RVV 1.0 with vector crypto, proven in mass production.
>9 SPECint2006/GHz · 2.5 GHz @ 12 nm
X200
Development complete 2026 · production 2027Optimized for AI inference: 14-stage, 6-wide out-of-order on TSMC 6 nm, with confidential computing, TSO, and coherent instruction cache. Not yet in a shipping kit.
>16 SPECint2006/GHz · 3.2 GHz @ 6 nm
Power Stone PMICs
The power half of the platform, built for the same boards.
P1
Multi-channel power management chip: 6 COT bucks, 12 LDOs, MTP NVM, with UVLO, OCP, OVP, and thermal shutdown. Ships with K1 on MUSE Paper.
P3
High-performance four-phase buck: 32 A sustained, 40 A peak, 91% peak efficiency, MTP-programmable timing, in a WLCSP 80-ball, 0.4 mm pitch package.
Compute IP
Licensed alongside the cores or already inside K3's virtualization and security blocks.
- T100 IOMMU
- Flexible integration for peripheral virtualization and acceleration.
- AIA
- An interrupt virtualization engine connecting devices and compute: up to 2047 MSI routes, 63 virtual-machine interrupt files, 1023 external interrupts at 256 priority levels.
- IOPMP
- A configurable foundation for high-performance bus security: Rapid-k model with 63 memory domains and 1024 entries, single-cycle latency on AXI4, ACE-Lite, and ACE5-Lite.
Software SDK
Two stacks, one runtime story: the silicon's capabilities exposed without bespoke kernel work.
AI Computer SDK
From a single board to a 48-chip cluster on one software stack.
- Runs 30B-parameter models locally on K3
- Standard CPU programming model, zero-cost migration
- Bianbu Linux and OpenHarmony support built in
- Hardware virtualization exposed end to end: CPU, memory, interrupts, IO
AI Robot SDK
Perception to actuation in one flow, on the robot's own silicon.
- Complete ROS 2 support: Humble and Jazzy, open source
- Independent real-time control domain with a dedicated interrupt and IO path
- Multi-channel EtherCAT and CAN-FD interface options
- Reinforcement-learning and multi-agent deployment, low-latency motion control
Ten official kits carry these chips, from an 85 × 56 mm board to a 2U cluster.
See the boards